1. Technical Field
The present invention relates to integrated circuits in general, and in particular to integrated circuits having multiple operating supply voltages. Still more particularly, the present invention relates to a method and apparatus for adjusting time delays of critical timing circuits within an integrated circuit having multiple operating supply voltages.
2. Description of the Prior Art
Some integrated circuits are required to operate at a wide range of supply voltages. Generally speaking, the operating speed of logic gates within an integrated circuit is typically higher when operating at a high voltage than at a low voltage. Thus, in most cases, it is usually favorable to have an integrated circuit operating at a high supply voltage; however, certain critical timing circuits require to be operated at a predetermined range of speed, and an operating speed beyond the predetermined range attributed from a high supply voltage may cause early mode timing failures to the critical timing circuits.
In the prior art, delay circuits are commonly added to critical timing circuits to ensure correct operating condition can be achieved even at a high supply voltage. Specifically, each of the delay circuits has a fixed amount of time delay, and correct timing in a critical timing circuit can be achieved by adding a delay circuit with the proper amount of time delay to the critical timing circuit. Even though the delay circuits can provide correct timing for the critical timing circuits when the integrated circuit is operating at a high supply voltage level, but the delay circuits also degrade the speed performance of all logic circuits within the integrated circuit during low supply voltage operations. Consequently, it would be desirable to provide an improved method and apparatus for adjusting time delays in critical timing circuits within an integrated circuit having multiple operating supply voltages.
In accordance with a preferred embodiment of the present invention, a voltage level detector and a delay means are coupled to a critical timing circuit of an integrated circuit that is capable of operating at multiple supply voltages. The voltage level detector detects a supply voltage at which the integrated circuit is operating. When the circuit operates at a high voltage level, the delay of the critical timing circuit increases. When the circuit operates at a low voltage level, the delay of the critical timing circuit decreases. Delays of the critical timing circuit are increased by introducing delay elements in the switching path and by disabling output current enhancement devices. Delays of the critical timing circuit are decreased by eliminating the delay elements and enabling the output current enhancement devices.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.